1. Field of the Invention
The present invention relates to an integrated circuit. More particularly, the present invention relates to a circuit structure of an integrated circuit.
2. Description of Related Art
With the blooming development of integrated circuit (IC) industry, miniaturization and integration of components are an inevitable trend, and have become important issues that different researchers focus on. Therefore, during manufacturing of the ICs or chips, electrical testing of the ICs or the chips at each processing stage is indispensable.
During fabrication of the ICs, processing conditions of the ICs are required to be adjusted to determine optimized processing parameters or component parameters, so as to improve a production yield of the ICs. Therefore, during the design of experiment (DOE) of research and development or manufacturing, a single wafer is required to be applied to each data point in an experiment. If a plurality of different parameters is required in the experiment, a number of wafers equivalent to that of the different parameters is required. However, the cost of the wafers (especially large-diameter wafers) is expensive when the processing parameters and the component parameters are optimized. Therefore, performing the aforementioned DOE on wafers will cost a lot of time and money.
Moreover, during the fabrication of the semiconductors, there are many factors which may influence the production yield. Therefore, during designing of the circuit, testing points or testing structure should be preset, according to the testing requirement of a finished product. When fabrication of the wafer is completed, wafer acceptance testing (WAT) based on a preset testing program is then performed, and problems that may occur during fabrication may be evaluated according to a testing result.
In a conventional technique, splitting test is generally performed on each lot of product, namely, a certain proportion of samples are selected from each lot of product, and testing is performed on the selected samples. Then, problems that may occur during fabrication will be evaluated according to the testing result, and the testing result is then statistically applied to all the products of the same lot.
However, if the splitting test is performed under poor lot conditions, the production yield may be reduced. Changing of a baseline during fabrication may cause a shifting of a process window, and therefore additional testing has to be performed. Moreover, the DOE and WAT are performed after the fabrication of the wafers is finished. Therefore, if abnormalities occurs during the fabrication, it cannot be solved immediately, and failure analysis or DOE of shifting can be performed only after the testing result is obtained. In this case, more testing time is required. Therefore, a quick and accurate testing method is highly desired.